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Micron First to Enable Ecosystem Partners With High-Capacity 128GB RDIMMs Using Monolithic 32Gb DRAM

Micron First to Enable Ecosystem Partners With High-Capacity 128GB RDIMMs Using Monolithic 32Gb DRAM

Micron Technology, Inc., demonstrated its industry leadership by announcing its 32Gb monolithic die-based 128GB DDR5 RDIMM memory featuring best-in-class performance of up to 8000 MT/s to support data center workloads and into the future. These high-capacity, high-speed memory modules are engineered to meet the performance and data-handling needs of a wide range of mission-critical applications in data center and cloud environments, including artificial intelligence (AI), in-memory databases (IMDBs) and efficient processing for multithreaded, multicore count general compute workloads. Powered by Micron’s industry-leading 1β (1-beta) technology, the 32Gb DDR5 DRAM die-based 128GB DDR5 RDIMM memory delivers the following enhancements over competitive 3DS through-silicon via (TSV) products:

  • more than 45% improved bit density
  • up to 24% improved energy efficiency
  • up to 16% lower latency2
  • up to a 28% improvement in AI training performance3

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“We are proud to set a new standard for high-capacity, high-speed memory in the data center with Micron’s 128GB DDR5 RDIMMs, which delivers the memory bandwidth and capacity required for increasingly compute-intensive workloads,” said Praveen Vaidyanathan, vice president and general manager of Micron’s Compute Products Group. “Micron continues to enable improvements to the data center ecosystem with early access to our advanced technologies and support in the design and integration of leading-edge high-capacity memory solutions.”

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Micron’s 32Gb DDR5 memory solution uses innovative die architecture choices for leading array efficiency and the densest monolithic DRAM die. Voltage domain and refresh management features help optimize the power delivery network providing much-needed energy efficiency improvements. Additionally, the die-dimension aspect ratio was optimized to advance the manufacturing efficiency of the 32Gb high-capacity DRAM die.

By leveraging AI-powered smart manufacturing methods to enable these world-class innovations, Micron’s 1β process technology node has achieved yield maturity in the fastest time in the company’s history.4 Micron’s 128GB RDIMMs will be shipping in platforms capable of 4800 MT/s, 5600 MT/s, and 6400 MT/s in 2024 and designed into future platforms capable of up to 8000MT/s.

“Our latest 4th Gen AMD EPYC processors will benefit from optimized memory capacity per core with Micron’s 128GB RDIMMs, which use 32Gb monolithic DRAM to provide an improved total cost of ownership solution for business-critical data enterprise workloads, such as AI, high-performance computing and virtualization,” said Dan McNamara, senior vice president and general manager, Server Business Unit, AMD. “As AMD advances compute with our next-gen EPYC processors, Micron’s 128GB RDIMMs will likely become one of the main memory options to deliver high-capacity and bandwidth per core capabilities to address the demands of memory-intensive applications.”

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“We look forward to Micron’s 32Gb-based 128GB RDIMM for the bandwidth and performance-per-watt solution benefits available in the server and AI systems market. Intel is evaluating this 32Gb memory offering for key DDR5 server platforms based on the resulting total cost of ownership benefits to cloud, AI and enterprise customers,” said Dr. Dimitrios Ziakas, vice president of Intel’s Memory and IO Technologies.

Micron 32Gb-DRAM die enables future expansion of the memory portfolio with enhanced bandwidth and energy-efficient MCRDIMM and JEDEC standard MRDIMM products in 128GB, 256GB and higher capacity solutions. With industry-leading process and design technology innovations, Micron offers a wide array of memory options across RDIMMs, MCRDIMMs, MRDIMMs, CXL and LP form factors to allow customers to integrate optimized solutions for AI and high-performance computing (HPC) applications that suit their needs for bandwidth, capacity and power optimization.

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