CacheQ Systems, Inc. announced GPU support for its QCC Acceleration Platform, a heterogenous compute development environment delivering faster performance and reduced development time for computer architectures including multi-core processors, GPUs and field programmable gate arrays (FPGA).
“Demand for hardware acceleration using GPUs and other heterogenous compute hardware is growing exponentially,” remarks Clay Johnson, CEO and co-founder of CacheQ Systems, developer of heterogeneous acceleration solutions. “Our goal is to simplify high-performance data center and edge-computing application development. The QCC Acceleration Platform meets that goal and will enable new solutions across a variety of applications, including life sciences, financial trading, government, oil and gas exploration and industrial IoT.”
The QCC Acceleration Platform Advantage
GPU deployment has advanced at a rapid pace in the last five years, and the yearly $25 billion dollar industry is expected to continue growing at approximately 33% CAGR through 2028.
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Heterogeneous compute systems such as multicore processors, GPUs as well as FPGAS attached to these processing systems have relied on software tools supported by hardware vendors and the open-source community. These tools traditionally relied upon software developers to pass information to the compilers to express parallelism in their code accomplished through hardware-specific APIs such as CUDA from NVIDIA, HIP from AMD, and oneAPI from Intel.
Other efforts attempt to support pragmas embedded in C, C++, and Fortran through OpenACC, OpenMP, and OpenCL. All require deep knowledge of the target hardware to control memory copy and synchronization events, create teams of threads, manually remove loop carry dependencies, race conditions, and to add summations to achieve performance and correct code behavior on parallel compute units.
CacheQ QCC is the first compiler platform to automatically extract parallelism from standard C, C++, and Fortran code without requiring the developer to explicitly communicate parallelism to the compiler. QCC automatically accelerates applications using a variety of hardware, exceeding the performance of pragma-based approaches and can approach hand-coded API solutions with minimal hardware knowledge. This allows a developer to write generic code and target high-performance hardware at compile time without refactoring code, or refactoring in such a way that it is not target hardware specific and is easily functionally verifiable.
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Based on the proprietary CacheQ virtual machine (CQVM), the QCC Acceleration Platform is a heterogenous compute development environment that converts serial high-level language (HLL) code into a parallel representation in less than 30 seconds for the most complex designs. It supports code profiling, utilization estimates, performance simulation, memory configuration and partitioning across a variety of compute engine processors including GPUs, x86, Arm and RISC-V, and FPGAs prior to generating a compute executable.
Features include a development environment with uniform drivers, protected containers and support for multiple boards from multiple vendors. Its design analysis offers profiling, performance simulation and memory activity reporting. An optimization capability adds code unrolling, user-driven memory configuration, and automatic and user-guided partitioning.
The FPGA implementation includes a resource estimator, pre-configured shells, multiple boards and parts, and implementation tool automation. The memory implementation supports automatic integration, multi-port/multi-access and striping.
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