PLDA, the leading developer of high-speed interconnect silicon IP, announced the launch of their XpressRICH™ PCI Express® (PCIe®) Controller IP for the PCIe 6.0 specification. The PCIe 6.0 specification provides an evolutionary step forward by doubling the data rate to 64 GT/s link rate negotiation. PCIe 6.0 architecture will be essential for SoC designers and system architects creating next generation chips that require the movement of large amounts of data within systems, in applications including:
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“With PLDA’s long and impressive track record of PCIe technology innovation, we are able to deliver PCIe 6.0’s groundbreaking technology, coupled with the ease-of-integration, robust ecosystem, and silicon-success rates that PLDA is known for.”
- HPC/Cloud Computing
- AI and Machine Learning
- Enterprise Storage
- Enterprise Networking
- Automotive
To support the doubling of bandwidth to 64 GT/s, PCIe 6.0 technology uses PAM4 modulation, which enables it to run 2 bits/cycle compared to the 1 bit/cycle with the previous NRZ modulation. To compensate for the higher BER (Bit Error Rate), XpressRICH for PCIe 6.0 architecture implements FEC (Forward Error Correction) combined with CRC (Cyclic Redundancy Check). XpressRICH for PCIe 6.0 architecture also supports the new L0p low power mode, enabling traffic to be transmitted on a reduced set of lanes, reducing power consumption without impacting traffic flow.
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To support configurability for XpressRICH users, PLDA has implemented a large number of features and ECN that can be fully parameterized through the included configuration assistant. Some of these configurable features include:
- Support for x1, x2, x4, x8, and x16 lane architectures
- Configurable data path
- Scalable internal data path based on selected configuration
- Support for end point, root port, dual mode, and switch port
- Support for multiple virtual channels (VCs) in FLIT and non-FLIT modes
- Parity protection for data path
- Multiple PIPE modes
- Support for SerDes Architecture
- Support for Single-Root I/O Virtualization (SR-IOV) Specification
- Configurable buffers (size and latency)
- Support for Clock Gating and Power Gating
- Backwards compatible to previous PCIe generations
- Optional IDE Security with AES-GCM encryption, decryption & authentication
According to Stephane Hauradou, CTO of PLDA, “Bandwidth efficiency is critical for data-intensive applications and PCIe 6.0 specification’s doubling of data rates and introduction of FLIT transport makes huge strides towards that.” Hauradou adds, “With PLDA’s long and impressive track record of PCIe technology innovation, we are able to deliver PCIe 6.0’s groundbreaking technology, coupled with the ease-of-integration, robust ecosystem, and silicon-success rates that PLDA is known for.”
XpressRICH for PCIe 6.0 Controller IP Interface Solutions and Availability:
PLDA has engaged with both our PHY Partner Ecosystem and our VIP Ecosystem to provide a complete offering featuring easy integration, low design risk, and a large choice of configurations and nodes that can only be obtained through third-party IP products.
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