Tackling extremely complex mobile chip designs on advanced nodes down to 2nm, Synopsys, Inc. has strengthened its AI-enhanced design collaboration with Arm as the company announces Arm Total Compute Solutions 2023 (TCS23) platform at Computex. Comprehensive EDA and IP solutions optimized for the highest levels of performance and power for Arm’s latest compute platform includes the Synopsys.ai full-stack AI-driven EDA suite, Synopsys Interface and Security IP and Synopsys Silicon Lifecycle Management PVT IP. These advancements build on decades of collaboration between the two companies to accelerate customers’ delivery of high-performance, efficient Arm-based SoCs for high-end smartphones and virtual/augmented-reality applications.
“The opportunity to unlock new magic on advanced mobile devices while constantly pushing performance and power-efficiency means design challenges become exponentially harder,” said Shankar Krishnamoorthy, GM of Synopsys EDA Group. “Collaborating with Arm to optimize our EDA and IP solutions enables mutual customers to tackle some of the toughest multi-die system integration challenges from design, IP integration and verification to software development. The addition of the Synopsys.ai EDA suite starts a new phase, where cooperative keystone companies, like Synopsys and Arm, align expertise to help mutual customers turbo-charge the delivery of their Arm-based SoC designs.”
“The new TCS23 platform delivers a suite of segment-specific technology, designed with the system in mind, so that our customers can tap into the compute performance required for the next generation of visual computing experiences,” said Chris Bergey, senior vice president and general manager, Client Line of Business, Arm. “Through our collaboration with Synopsys, and its full-stack AI-driven EDA suite and silicon-proven IP solutions, customers will now be able to push performance further than ever before and maximize the benefits of the most advanced nodes.”
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Synopsys addresses the complex, system-level challenges of hierarchical implementation for high-performance cores without performance, power and runtime compromises through advanced differentiated features such as multi-source clock tree synthesis, intelligent budgeting, timing driven pin assignment, seamless constraints push down and transparent hierarchy optimization.
The Synopsys system-level solutions for TCS23 include:
- Synopsys.ai full-stack AI-driven EDA suite, which taps into the power of AI from system architecture through manufacturing to optimize power, performance and area (PPA) and enhance time to market.
- Synopsys Verification Family, which accelerates architecture exploration, software development and verification throughput for Arm SoCs containing Arm Cortex-X4, Cortex-A720 and Cortex-A520 CPUs and Immortalis-G720 and Mali-G720 GPUs. Early adopters of TCS23 are using Synopsys virtual prototypes with Arm Fast Models, Synopsys hardware-assisted verification and verification IP for the latest Arm AMBA interconnect to deliver SoCs to market faster.
- Synopsys Interface and Security IP for PCI Express 6.0 with Integrity and Data Encryption (IDE), https://www.synopsys.com/designware-ip/interface-ip/cxl.htmlCXL 3.0 with IDE, DDR5 with Inline Memory Encryption (IME) and UCIe, all of which are optimized for performance with Arm-specific features and for pre-silicon interoperability with Arm Cores to minimize risk and accelerate time to market.
- Synopsys Silicon Lifecycle Management Family PVT monitor IP, which can be integrated into Arm cores to monitor chip health from development to the field to measure and optimize performance.
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