The Katana edge SoC accelerates development of AI vision and sensor-fusion applications for the IoT.
In the video above, Electronic Design’s Bill Wong talks with Syed Alam, the Global High Tech Industry Lead at Accenture, about the advent of chiplets and how they may help overcome the challenges with Moore’s Law. The article below goes into more detail about the technology.
For the past couple of decades, most semiconductor advances, capabilities, and innovations have happened on the front end. This technological progress has been accompanied by increasingly more complex designs and smaller geometries, currently culminating at the 3-nm process node. Lately, though, achieving Moore’s Law has become more challenging and costly, to the point where building a 5-nm chip is now more costly than building 10- and 7-nm chips combined.
As the benefits of scaling continue to decrease with each new node, chipmakers are turning back to a concept nearly a decade old: Rather than manufacture a chip on a single piece of silicon, they’re combining individual functional die, also known as “chiplets,” which might be the next frontier in achieving Moore’s Law and advanced manufacturing at scale.
CIO INFLUENCE News: The EdgeCore Digital Infrastructure Delivers Dense, Scalable, and Certain Execution
Top Architectures Involved in Chiplet Design
As previously mentioned, manufacturing a chip on a single piece of silicon (commonly referred to as systems-on-chips or SoCs) has led to skyrocketing costs. One path to achieve the same level of performance at a fraction of the cost is by combining chipsets with different functions. There are three mainstream architecture designs for compiling chiplets:
- Fan-out: Fan-out utilizes dice and redistribution layers to combine different chiplets. Fan-out isn’t as fast or power efficient as other architecture systems, but it’s more easily testable and therefore has a faster time-to-market.
- 2.5D: 2.5D packaging methodology uses an interposer for stacked inter-chiplet communication, leading to a higher communication rate. It can be paired with stacked memory modules to create high-performance modules. However, the interposers that enable 2.5D architecture are expensive relative to the other methods.
- 3D: 3D is the same general idea as 2.5D with chip stacking, but it involves stacking logic on logic chiplets with through silicon vias (TSVs) to yield the highest-performance chip designs.
CIO INFLUENCE News: Omdia : No Code Low Code Solutions Unlock Application Development Bottleneck
[To share your insights with us, please write to sghosh@martechseries.com]
