Intel’s latest innovations, presented at the 2023 IEEE International Electron Devices Meeting, emphasize the company’s commitment to advancing Moore’s Law. These innovations include developments in 3D stacked CMOS transistors, incorporating backside power and direct backside contacts. Additionally, Intel showcased progress in scaling pathways for backside power delivery, specifically with backside contacts. Intel achieved a significant milestone by demonstrating large-scale 3D monolithic integration of silicon transistors with gallium nitride (GaN) transistors on the same 300mm wafer, a departure from traditional packaging methods. These breakthroughs indicate a promising future for Intel’s process roadmap.
“As we enter the Angstrom Era and look beyond five nodes in four years, continued innovation is more critical than ever. At IEDM 2023, Intel showcases its progress with research advancements that fuel Moore’s Law, underscoring our ability to bring leading-edge technologies that enable further scaling and efficient power delivery for the next generation of mobile computing.” –SANJAY NATARAJAN, senior vice president and general manager of Components Research at Intel
Intel’s Pioneering Transistor Innovations Unveiled at IEDM 2023
The semiconductor advancements by Intel’s strides in transistor scaling and backside power mark pivotal progress toward meeting the skyrocketing demand for high-powered computing. These innovations underscore the company’s consistent commitment to propelling the semiconductor industry forward and upholding the enduring principle of Moore’s Law.
Intel’s Components Research division stands as a trailblazer, continually pushing the engineering boundaries by spearheading transformative approaches. Stacking transistors, amplifying backside power capabilities, and integrating transistors with diverse materials on a single wafer exemplify Intel’s cutting-edge strides.
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The recent unveiling at IEDM 2023 reinforces Intel’s dedication to exploring novel methodologies for augmenting transistor density on silicon while enhancing overall performance. By focusing on stacking transistors with unprecedented efficiency and implementing groundbreaking backside power and contact solutions, Intel is poised to redefine transistor architecture technology. With advancements in backside power delivery and the integration of innovative 2D channel materials, Intel’s vision extends Moore’s Law to encompass a trillion transistors on a single package by 2030.
Intel’s groundbreaking research is at the forefront of this innovation, demonstrating an industry-first achievement: the vertical stacking of complementary field effect transistors (CFET) at an impressively scaled gate pitch down to 60 nanometers (nm). This pioneering approach maximizes area efficiency and performance benefits and integrates backside power and direct backside contacts. This milestone showcases Intel’s supremacy in gate-all-around transistors and positions the company as a vanguard, surging ahead of industry competition and spearheading the future of semiconductor evolution.
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Advances in Transistor Technology
Intel is breaking new ground in transistor technology, showcasing its latest research at IEDM 2023. The company has achieved an industry first by vertically stacking complementary field-effect transistors (CFET) with a scaled gate pitch down to 60 nanometers (nm). This demonstrates Intel’s leadership in gate-all-around transistors and innovation beyond RibbonFET, positioning it ahead of competitors. The research also introduces PowerVia, slated to be manufacturing-ready in 2024, as the first implementation of backside power delivery. Intel has successfully integrated silicon transistors with gallium nitride (GaN) transistors on the same 300 mm wafer, showcasing a large-scale integrated circuit solution named “DrGaN,” for power delivery.
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Additionally, Intel is advancing research and development in the 2D transistor space for future scaling in line with Moore’s Law, including prototypes of high-mobility transition metal dichalcogenide (TMD) transistors. The company will present the world’s first gate-all-around 2D TMD PMOS transistor and the first 2D PMOS transistor on a 300 mm wafer. These achievements underscore Intel’s commitment to pushing the boundaries of semiconductor technology.
FAQs
1. What are the key innovations highlighted by Intel at IEDM 2023?
Intel unveiled advancements in 3D stacked CMOS transistors with backside power and direct backside contacts. Notably, they achieved large-scale silicon and GaN transistor integration on a 300mm wafer.
2. How does Intel’s Components Research division contribute to these innovations?
Intel’s Components Research division pioneers transformative approaches by stacking transistors efficiently, integrating diverse materials on a single wafer, and focusing on backside power advancements and transistor architecture.
3. What significance do these innovations hold for Intel’s semiconductor roadmap?
These breakthroughs signify Intel’s commitment to advancing Moore’s Law, enhancing transistor density on silicon, and enabling more powerful computing while aiming for a trillion transistors on a single package by 2030.
4. What specific achievements did Intel demonstrate in transistor technology at IEDM 2023?
Intel showcased industry-first achievements in vertically stacking complementary field-effect transistors (CFET) with a scaled gate pitch down to 60 nanometers. They introduced PowerVia for backside power delivery and integrated silicon and GaN transistors on the same wafer.
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