Alphawave Semi, a global leader in high-speed connectivity for the world’s technology infrastructure, announced two successful tapeouts on TSMC’s most advanced 3nm process of its High Bandwidth Memory 3 (HBM3) PHY and Universal Chiplet Interconnect Express (UCIe) PHY IPs, paving the way for a new generation of chiplet-enabled silicon platforms, tailored for hyperscaler and data infrastructure customers. Notably, Alphawave Semi is the first company to announce UCIe PHY IP supporting faster die-to-die data rates of 24Gbps per lane, delivering an impressive bandwidth of 7.9 Terabits per second over a tight space of a millimeter of a chip beachfront.
The TSMC 3nm process technology is vital for creating advanced chips that can effectively handle the exponential surge in data generated by AI, with demands for more compute, memory bandwidth, I/O speeds, and energy efficiency.Alphawave Semi’s 3nm chiplet-enabled custom silicon platform is built on flexible and customizable connectivity IP.Customers benefit from Alphawave Semi’s application-optimized IP subsystems and experience with the TSMC 3DFabric ecosystem to integrate advanced interfaces such as CXL, UCIe, HBMx, and Ethernet onto custom chips and chiplets.
HBM3: Satisfying the Increasing Demand for Bandwidth
In AI and high-performance computing (HPC) systems where the key performance indicator is Memory Bandwidth per Watt, HBM emerges as a top choice, offering the highest bandwidth, optimal area footprint, and superior power efficiency.
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The Alphawave Semi HBM3 PHY IP targets leading-edge high-performance memory interfaces up to 8.6Gbps and 16 channels, operating at very low power. Customers are deploying complete HBM subsystem solutions from Alphawave Semi which integrate the HBM PHY with a versatile JEDEC-compliant, highly configurable HBM controller that can be fine-tuned to maximize the efficiency for application-specific AI and high-performance computing workloads.
UCIe: Advancing toward a universal chiplet ecosystem
Chiplets are poised to dominate the world of high-performance data center AI semiconductors due to their numerous advantages over traditional monolithic designs, including improved flexibility, scalability, power efficiency, and cost-effectiveness. Leveraging advances in multi-die packaging, system designers can mix and match pre-built or customized compute, memory, and IO chiplets in different process nodes, creating complete Systems-in-a-Package (SIPs), paving the way for SiP to become the system motherboard of the future.
The Alphawave Semi UCIe PHY IP is an extremely power efficient, low-latency, and highly reliable interface IP, designed to connect chiplet silicon die in the same package at top speeds of 24Gbps per wire while consuming less than 0.3 picoJoules of power per bit. The UCIe PHY can be paired with Alphawave Semi’s PCIe, CXL, and streaming controllers to support the full UCIe protocol stack. The PHY can be configured to support advanced packaging such as TSMC’s Chip-on-Wafer-on-Substrate (CoWoS®) and Integrated Fan-Out (InFO) which maximize signal densities, as well as organic substrates for a more cost-effective solution.
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Praveen Vaidyanathan, vice president and general manager of Micron’s Compute Products Group, said, “Generative AI is pushing the performance requirements in data centers, fueling the demand for advanced memory solutions like HBM3 to provide very high bandwidth with improved energy efficiency.The tape-out of Alphawave Semi’s HBM3 solution in TSMC’s most advanced 3nm process is an exciting new milestone. It allows cloud service providers to leverage Alphawave Semi’s HBM3 IP subsystems and custom silicon capabilities to accelerate AI workloads in next-generation data center infrastructure.”
Dr. Debendra Das Sharma, Chairman, UCIe Consortium, said, “We’re excited to see Alphawave Semi tape out a 24Gbps/lane UCIe IP in a 3nm process. This milestone demonstrates how UCIe can help fuel innovation through leading-edge chiplet connectivity, and we welcome Alphawave Semi’s commitment to delivering IPs that support the development of an open chiplet ecosystem.”
“With our vertically integrated semiconductor focus, we’re excited to deliver a comprehensive 3nm chiplet connectivity platform for hyperscaler and data-infrastructure customers to keep pace with the surge in data-intensive applications like generative AI,” said Tony Pialis, CEO and co-founder of Alphawave Semi. “Our latest 3nm tapeouts are a testament to Alphawave Semi’s dedication to technology leadership in connectivity and our collaborative efforts in fostering an open chiplet ecosystem.”
“We are excited to announce simultaneous tapeouts of our HBM3 IP and our industry-first 24GT/s UCIe IP for TSMC’s 3nm technology, which are key enablers of our I/O chiplet portfolio,” said Mohit Gupta, SVP and GM, Custom Silicon and IP, Alphawave Semi. “Our top hyperscaler and datacenter infrastructure customers can now mix and match high-performance 3nm custom SoCs with IO connectivity chiplets from Alphawave Semi providing a new level of flexibility and scalability for their AI-enabled systems.”
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